3d7 110 doc #96005 data delay devices, inc. 1 12/2/96 3 mt. prospect ave. clifton, nj 07013 monolithic 10-tap fixed delay line (series 3d7110) features all-silicon, low-power cmos technology ttl/cmos compatible inputs and outputs vapor phase, ir and wave solderable auto- insertable (dip pkg.) low ground bounce noise leading- and trailing-edge accuracy delay range: .75 through 80ns delay tolerance: 5% or 1ns temperature stability: 3% typical (0c-70c) vdd stability: 1% typical (4.75v-5.25v) minimum input pulse width: 15% of total delay 14-pin gull-wing and 16-pin soic available as drop-in replacements for hybrid delay lines functional description the 3d7110 10-tap delay line product family consists of fixed-delay cmos integrated circuits. each package contains a single delay line, tapped and buffered at 10 points spaced uniformly in time. tap-to-tap (incremental) delay values can range from 0.75ns through 8.0ns. the input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. the 3d7110 is ttl- and cmos- compatible, capable of driving ten 74ls-type loads, and features both rising- and falling-edge accuracy. the all-cmos 3d7110 integrated circuit has been designed as a reliable, economic alternative to hybrid ttl fixed delay lines. it is offered in a standard 14-pin auto- insertable dip and space saving surface mount 14- and 16-pin soic packages. packages 14 13 12 11 10 9 8 1 2 3 4 5 6 7 in n/c o2 o4 o6 o8 gnd vdd o1 o3 o5 o7 o9 o10 3d7110 dip 3d7110g gull-wing (300 mil) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 in n/c n/c o2 o4 o6 o8 gnd vdd n/c o1 o3 o5 o7 o9 o10 3d7110s soic (300 mil) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 in n/c o2 o4 o6 o8 gnd vdd o1 o3 o5 o7 o9 o10 3d7110d soic (150 mil) data delay devices, inc. 3 (for mechanical data, see case dimensions document) pin descriptions in delay line input o1 tap 1 output (10%) o2 tap 2 output (20%) o3 tap 3 output (30%) o4 tap 4 output (40%) o5 tap 5 output (50%) o6 tap 6 output (60%) o7 tap 7 output (70%) o8 tap 8 output (80%) o9 tap 9 output (90%) o10 tap 10 output (100%) vcc +5 volts gnd ground table 1: part number specifications part number tolerances input restrictions dip-14 3d7110 3d7110g soic-14 3d7110d soic-16 3d7110s total delay ( ns) tap-tap delay ( ns) max operating frequency absolute max oper. freq. min operating pulse width absolute min oper. p.w. -.75 -.75 -.75 6.75 1.0* 0.75 0.4 28.4 mhz 166.7 mhz 17.6 ns 3.00 ns -1 -1 -1 9.0 1.0* 1.0 0.5 23.8 mhz 166.7 mhz 21.0 ns 3.00 ns -1.5 -1.5 -1.5 13.5 1.0* 1.5 0.7 18.0 mhz 166.7 mhz 27.8 ns 3.00 ns -2 -2 -2 18.0 1.0* 2.0 0.8 14.5 mhz 166.7 mhz 34.5 ns 3.00 ns -2.5 -2.5 -2.5 22.5 1.1* 2.5 1.0 18.2 mhz 125.0 mhz 27.5 ns 4.00 ns -4 -4 -4 36.0 1.8* 4.0 1.3 8.33 mhz 133.3 mhz 60.0 ns 6.00 ns -5 -5 -5 50.0 2.5 5.0 1.5 6.67 mhz 66.7 mhz 75.0 ns 7.50 ns -8 -8 -8 80.0 4.0 8.0 1.5 4.17 mhz 41.7 mhz 120.0 ns 12.0 ns * total delay referenced to tap1 output; input-to-tap1 = 5.0ns 1.0ns note: any dash number between .75 and 8 not shown is also available. 1996 data delay devices
3d7110 doc #96005 data delay devices, inc. 2 12/2/96 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com application notes operational description the 3d7110 ten-tap delay line architecture is shown in figure 1. the delay line is composed of a number of delay cells connected in series. each delay cell produces at its output a replica of the signal present at its input, shifted in time. the delay cells are matched and share the same compensation signals, which minimizes tap-to- tap delay deviations over temperature and supply voltage variations. input signal characteristics the frequency and/or pulse width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. the reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. therefore a maximum and an absolute maximum operating input frequency and a minimum and an absolute minimum operating pulse width have been specified. operating frequency the absolute maximum operating frequency specification, tabulated in table 1 , determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. the maximum operating frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed. to guarantee the table 1 delay accuracy for input frequencies higher than the maximum operating frequency , the 3d7110 must be tested at the user operating frequency. therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. the programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all. nevertheless, it is strongly recommended that the engineering staff at data delay devices be consulted. operating pulse width the absolute minimum operating pulse width (high or low) specification, tabulated in table 1 , determines the smallest pulse width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. the minimum operating pulse width (high or low) specification determines the smallest pulse width of the delay line input signal for which the output delay accuracy tabulated in table 1 is guaranteed. to guarantee the table 1 delay accuracy for input pulse width smaller than the minimum operating pulse width , the 3d7110 must be tested at the user operating pulse width. therefore, to facilitate production and device identification, the part number will include a vdd o1 in o2 o3 o4 temp & vdd compensation gnd figure 1: 3d7110 functional diagram 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% o5 o6 o7 o8 o9 o10
3d7 110 doc #96005 data delay devices, inc. 3 12/2/96 3 mt. prospect ave. clifton, nj 07013 application notes (cont?d) custom reference designator identifying the intended frequency and duty cycle of operation. the programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy, if at all. nevertheless, it is strongly recommended that the engineering staff at data delay devices be consulted. power supply and temperature considerations the delay of cmos integrated circuits is strongly dependent on power supply and temperature. the monolithic 3d7110 programmable delay line utilizes novel and innovative compensation circuitry to minimize the delay variations induced by fluctuations in power supply and/or temperature. the thermal coefficient is reduced to 600 ppm/c , which is equivalent to a variation , over the 0c-70c operating range, of 3% from the room-temperature delay settings and/or 1.0ns , whichever is greater. the power supply coefficient is reduced, over the 4.75v-5.25v operating range, to 1% of the delay settings at the nominal 5.0vdc power supply and/or 1.5ns , whichever is greater. it is essential that the power supply pin be adequately bypassed and filtered. in addition, the power bus should be of as low an impedance construction as possible. power planes are preferred. device specifications table 2: absolute maximum ratings parameter symbol min max units notes dc supply voltage v dd -0.3 7.0 v input pin voltage v in -0.3 v dd +0.3 v input pin current i in -1.0 1.0 ma 25c storage temperature t strg -55 150 c lead temperature t lead 300 c 10 sec table 3: dc electrical characteristics (0c to 70c, 4.75v to 5.25v) parameter symbol min max units notes static supply current* i dd 30 ma high level input voltage v ih 2.0 v low level input voltage v il 0.8 v high level input current i ih 1 m a v ih = v dd low level input current i il 1 m a v il = 0v high level output current i oh -4.0 ma v dd = 4.75v v oh = 2.4v low level output current i ol 4.0 ma v dd = 4.75v v ol = 0.4v output rise & fall time t r & t f 2 ns c ld = 5 pf *i dd (dynamic) = 10 * c ld * v dd * f input capacitance = 10 pf typical where: c ld = average capacitance load/tap ( pf) output load capacitance (c ld ) = 25 pf max f = input frequency ( ghz)
3d7110 doc #96005 data delay devices, inc. 4 12/2/96 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com silicon delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c r load : 10k w 10% supply voltage ( vcc): 5.0v 0.1v c load : 5pf 10% input pulse: high = 3.0v 0.1v threshold: 1.5v (rising & falling) low = 0.0v 0.1v source impedance: 50 w max. rise/fall time: 3.0 ns max. (measured between 0.6v and 2.4v ) pulse width: pw in = 1.25 x total delay period: per in = 2.5 x total delay note: the above conditions are for test only and do not in any way restrict the operation of the device. 10k w 470 w 5pf device under test digital scope out1 out2 out4 out3 out trig in ref trig figure 2: test setup device under test (dut) digital scope/ time interval counter pulse generator computer system printer in out5 out6 out8 out7 out10 out9 figure 3: timing diagram t plh t phl per in pw in t rise t fall 0.6v 0.6v 1.5v 1.5v 2.4v 2.4v 1.5v 1.5v v ih v il v oh v ol input signal output signal
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